题  目: High-Speed, Low-Power Pipelined SAR ADCs with Passive Residue Transfer and Dynamic Amplifier

主讲人: Huang Hai (Dr.)

主持人: Qiang Li（Prof.）

简  介：

Hai Huang received the B.S. degree and the M.Sc. degree in electrical engineering from the University of Electronic Science and Technology of China, Chengdu, China, in 2010 and 2013. He is currently working towards the Ph.D. degree at the University of Texas at Dallas, Richardson, TX, USA. From June 2015 to September 2015, he was an intern with Analog Devices, MA, USA, where he investigated ring amplifiers and dynamic amplifiers. His main research interests include data converters and emerging low power amplifiers, where he has published in the premier conference of ISSCC. He received the first prize of National Undergraduate Electronic Design Contest in Sichuan section in 2009. He also was a recipient of the Analog Devices Outstanding Student Designer Award in 2014.

In this talk, a pipelined SAR architecture with passive residue transfer will firstly be reported to push the speed limit of conventional SAR ADC. We will then discuss a PVT-stabilized dynamic amplification technique for stable residue production in pipelined SAR ADCs. With above techniques, two high-speed, low-power pipelined SAR ADCs will be presented as design examples.

Welcome to attend!

时间: 2016年12月7日（周三）上午10:00

地点: 沙河校区微固楼137会议室

电子科技大学低功耗集成电路与系统研究所